1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly relates to a layout of a semiconductor memory device having a redundant memory cell that replaces a defective normal memory cell.
2. Description of Related Art
Because a semiconductor memory device represented by DRAM (Dynamic Random Access Memory) has many memory cells, it is difficult to manufacture all the memory cells without a defect. Thus, besides normal memory cells, redundant memory cells that can replace the normal memory cells when they are defective are generally prepared beforehand (see Japanese Patent Application Laid-open Nos. 2000-268596 and H6-314498). Such a semiconductor memory device uses a repair determining circuit for determining whether an address to which access is requested is a defective address, and a redundant driver circuit for accessing a redundant memory cell when the address is determined as a defective address by the repair determining circuit.
First, when an address is supplied from outside, whether the address is a defective address is determined by the repair determining circuit. Subsequently, either a driver circuit or a redundant driver circuit starts operating based on the result of the determination, and thereby, the access is executed to one of the normal memory cell and the redundant memory cell.
However, determination by the repair determining circuit takes a relatively long time. Thus, for example, in a DRAM, there is a problem that a period tRCD from inputting of an active command indicating an input timing of a row address until inputting of a read or write command indicating an input timing of a column address is rate-controlled by a determining operation performed by the repair determining circuit, and thus a random RAS access is delayed.
To solve such a problem, there is a method for a parallel execution of some of access operations to the normal memory cells and the determining operation by the repair determining circuit (see Japanese Patent Application Laid-open No. 2000-293998). According to this method, the access speed at the row side is improved, and thus the period tRCD can be shortened. In the case where a defective address is detected by the repair determining circuit, the normal memory cells are not accessed, thereby preventing a state that a plurality of memory cells are selected simultaneously. Specifically, after activating a main word line and before activating a sub-word line, only the sub-word lines corresponding to the redundant memory cells are activated by resetting the main word lines corresponding to the normal memory cells.
As described above, in a general semiconductor memory device, the determining operation by the repair determining circuit is performed first, and after its completion, the decode operation by the predecoder is performed. Thus, it is general that the repair determining circuit is placed near an address latch circuit while the predecoder is arranged near a main decoder. However, in a case of the semiconductor memory device described in Japanese Patent Application Laid-open No. 2000-293998, there is a problem that when some of the access operations to the normal memory cells are executed in parallel with the determining operation by the repair determining circuit, the distance from the repair determining circuit to the main decoder becomes considerably long as compared to the distance from the predecoder to the main decoder when the general layout, is adopted, and the effect of the high-speed access realized by the parallel operation is reduced.